• DocumentCode
    2875541
  • Title

    An LSI adaptive array processor

  • Author

    Sudo, Toshio ; Nakashima, Takayoshi ; Aoki, Masaki ; Kondo, Toshiaki

  • Author_Institution
    NTT Musashino Electrical Communication Laboratory, Tokyo, Japan
  • Volume
    XXV
  • fYear
    1982
  • fDate
    10-12 Feb. 1982
  • Firstpage
    122
  • Lastpage
    123
  • Abstract
    This report will cover the design of an array of 8×8 lb processors implemented in 3μ-m NMOS technology with 81,000 transistors, providing two dimensional data processing.
  • Keywords
    Adaptive arrays; Arithmetic; Data processing; Laboratories; Large scale integration; Logic arrays; Logic design; Multiplexing; Size control; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1982 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1982.1156412
  • Filename
    1156412
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2875541