An Enhanced HyperTransport Controller with Cache Coherence Support for Multiple-CMP

Author

Wang, Huandong ; Tang, Dan ; Gao, Xiang ; Chen, Yunji

Author_Institution

Inst. of Comput. Technol., Chinese Acad. of Sci., Beijing, China

fYear

2009

fDate

9-11 July 2009

Firstpage

215

Lastpage

218

Abstract

HyperTransport link is a high performance IO interface for system connection. In this paper, the architecture of a HyperTransport interface is introduced. This HyperTransport interface realizes efficient HT-AXI bidirectional transformation, where AXI is a popular bus protocol in SOC architectures. Furthermore, this HyperTransport interface provides dedicated hardware support for cache coherence protocol. Through this HyperTransport interface, Godson-3A multi-core processor chips can be interconnected together to form a 4-16 core CC-NUMA system or a large-scale NCCNUMA system. The verification of the HyperTransport interface is also presented.

Keywords

cache storage; microprocessor chips; system buses; system-on-chip; CC-NUMA system; Godson-3A multicore processor chips; HT-AXI bidirectional transformation; HyperTransport interface; IO interface; NCCNUMA system; SOC architectures; bus protocol; cache coherence protocol; enhanced HyperTransport controller; multiple-CMP; system connection; Bandwidth; Cache storage; Computer architecture; Filters; Hardware; Logic; Multicore processing; Physical layer; Protocols; Switches; Cache coherence; HyperTransport; Interconnect;

fLanguage

English

Publisher

ieee

Conference_Titel

Networking, Architecture, and Storage, 2009. NAS 2009. IEEE International Conference on

Conference_Location

Hunan

Print_ISBN

978-0-7695-3741-2

Type

conf

DOI

10.1109/NAS.2009.46

Filename

5197325