Memory Footprint Reduction for FPGA Routing Algorithms

In this paper, we present a technique to reduce the run-time memory footprint of FPGA routing algorithms. These algorithms require a representation of the physical routing resources and programmable connections on the device; this representation dominates the storage requirements of FPGA routers. We show that by taking advantage of the tile-based nature of FPGAs, we can reduce the amount of information that must be explicitly represented, leading to significant memory savings. To make our proposal concrete, we applied it to the routing algorithm in VPR and quantified the impact on run-time memory footprint, and place and route compile-time. We found that a memory reduction of 5X to 13X could be achieved at a routing runtime penalty of 2.26X and an overall place-and-route runtime penalty of 1.28X.