SOC implementation of wave-pipelined circuits

In the literature, wave-pipelining is proposed as one of the techniques for increasing the operating frequency of the digital circuits. Higher operating frequencies can be achieved in wave-pipelined (WP) circuits, by adjusting the clock periods and clock skews so as to latch the outputs of combinational logic circuits at the stable periods. Major contributions of this paper are the proposal for the use of soft-core processor for the automation of the above tasks, and the superiority of the WP circuits with regard to power dissipation. The proposed scheme is evaluated by using two circuits: filters using distributed arithmetic algorithm (DAA) and a sine wave generator using coordinate rotation digital computer (CORDIC) algorithm. Both the circuits are studied by adopting three different schemes: wave-pipelining, pipelining and non-pipelining. The system-on-chip (SOC) approach is adopted for implementation on Altera field programmable gate arrays (FPGAs) based SOC kits with Nios II soft-core processor. From the implementation results, it is verified that the WP circuits are faster compared to non-pipelined circuits. The pipelined circuits are found to be faster than the WP circuits and this is achieved at the cost of increase in area and power. For the power dissipation, when both pipelined and WP circuits are operated at the same frequency, the former dissipates more power for circuits with higher word sizes and for medium taps filters. From the implementation results, it is verified that the superiority of the power dissipation of the WP circuits depends not only on the area but also on the logic depth of the circuit. This observation is made for the first time for the WP circuits.