• DocumentCode
    2876323
  • Title

    A 70ns high density CMOS DRAM

  • Author

    Chwang, R. ; Choi, Michael ; Creek, D. ; Stern, Sebastian ; Pelley, P. ; Schutz, J. ; Bohr, M. ; Warkentin, P. ; Yu, Kaiyuan

  • Author_Institution
    Intel Corp., Aloha, OR, USA
  • Volume
    XXVI
  • fYear
    1983
  • fDate
    23-25 Feb. 1983
  • Firstpage
    56
  • Lastpage
    57
  • Abstract
    A 64K DRAM, processed in N-well CMOS technology with 137μm2double poly P-channel memory cells, will be reported. Access time is 70ns at 150mW. Operating margins, SER and redundancy repairability will be discussed.
  • Keywords
    CMOS technology; Circuits; Clocks; DRAM chips; Decoding; Error analysis; Latches; MOS devices; Random access memory; Redundancy;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1983.1156456
  • Filename
    1156456
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2876323