Title :
A virtual memory management chip with program debugging support
Author :
Lavi, Y. ; Mizrachi, A.
Author_Institution :
National Semiconductor Ltd., Herzlina, Israel
Abstract :
This report will cover a 20K device memory management NMOS chip for a 32b microprocessor, which accesses memory-based translation tables and maintains 32 translation entries in an associative cache memory in less than 100ns.
Keywords :
Associative memory; Debugging; Logic; MOS devices; Memory management; Protection; Registers; Semiconductor device packaging; Technology management; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156460
