DocumentCode
2876391
Title
A virtual memory management chip with program debugging support
Author
Lavi, Y. ; Mizrachi, A.
Author_Institution
National Semiconductor Ltd., Herzlina, Israel
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
26
Lastpage
27
Abstract
This report will cover a 20K device memory management NMOS chip for a 32b microprocessor, which accesses memory-based translation tables and maintains 32 translation entries in an associative cache memory in less than 100ns.
Keywords
Associative memory; Debugging; Logic; MOS devices; Memory management; Protection; Registers; Semiconductor device packaging; Technology management; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156460
Filename
1156460
Link To Document