DocumentCode :
2876483
Title :
A sub 100ns 256Kb DRAM
Author :
Nakano, T. ; Yabu, T. ; Noguchi, E. ; Shirai, Keigo ; Miyasaka, K.
Author_Institution :
Fujitsu, Ltd., Kawasaki, Japan
Volume :
XXVI
fYear :
1983
fDate :
23-25 Feb. 1983
Firstpage :
224
Lastpage :
225
Abstract :
A 256K DRAM with nibble-mode and 
before 
refresh will be described. Triple-poly-si processing is used only with 2.5μ layout rules for a die size of 34.1mm2.
before refresh will be described. Triple-poly-si processing is used only with 2.5μ layout rules for a die size of 34.1mm2.Keywords :
Capacitors; Circuit testing; Electronics packaging; Fuses; Joining processes; Pins; Random access memory; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1983.1156467
Filename :
1156467
Link To Document :
