Title :
Automatically generated area, power and delay optimized ALUs
Author :
Montoye, R. ; Cook, Peter
Author_Institution :
University of Illinois, Urbana-Champaign, IL, USA
Abstract :
This paper will describe a CAD program which automatically produces an optimized ALU from a family of carry-look-ahead ALU designs, and produces the mask data from a layout rule independent description. A 34b ALU has been automatically synthesized using the program and simulated in 1.4μm NMOS with a limiting delay in nominal technology of about 16ns.
Keywords :
Adders; Arithmetic; Costs; Delay; Design automation; Merging; Power generation; Signal generators; Silicon; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1983.1156473
