A Power Configurable Block Array Connected in Series as First Prototype Flex Power FPGA Chip

First prototype flex power FPGA chip is presented. Basic concept of flex power FPGA is to control speed/power trade-off relationship flexibly by assigning the proper threshold voltage generated from body-bias control circuits to transistors. An experimental chip, which implements a power configurable block array connected in series having minimal indispensable functions to flex power FPGA, i.e. circuit configurability and power configurability, was fabricated in 90 nm standard CMOS technology with triple-well option for the first time. As evaluation results of the static power saving ability and operating speed controllability, the concept of flex power FPGA is proved.