DocumentCode
2876775
Title
A 5000-gate bipolar masterslice LSI with 500ps loaded gate delay
Author
Suzuki, M. ; Horiguchi, Shogo ; Sudo, Toshio
Author_Institution
Nippon Tel.-Tel. Musashino Electrical Communication Laboratory, Tokyo, Japan
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
150
Lastpage
151
Abstract
A fully ECL compatible bipolar master slice LSI with a loaded gate delay of 500ps and power dissipation of less than 6W will be reported. A 1.5μm design rule bipolar process employing three levels of metalization has been utilized.
Keywords
Aluminum; Circuits; Delay; Large scale integration; Logic; Power dissipation; Power supplies; Regulators; Voltage; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156484
Filename
1156484
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