A Portable Co-Verification System Which Generates Testbench Automatically

Verification is the most time consuming process in an LSI development. The SoC and other complex embedded systems consist of hardware and software. Because of the strong demand of shorting ´the time to market,´ it becomes important to verify the software on the under the development hardware. We call this verification process as ´Co-Verification.´ One of the hardware verification technique is an emulation which implements equivalent under the test logic circuit with FPGA. We can speed up the logic behavior of Co-Verification with emulation technique. We call this ´Co-Emulation.´ In contrast to Co-Emulation, we call ´Co-Simulation´ when all verification is carried out with software. We developed a Co-Verification system which supports Co-Emulation and/or Co-Simulation. Our system only requires an FPGA board with PCI interface and a Linux running PC. We use C++ and SCE-MI(Standard Co-Emulation Modeling Interface) API for the testbench language which are open standards for verification. Our system inspects the DUT (design under the test), and automatically generates the testbench skelton and associated hardware that includes the PCI interface and the SCE-MI transactors. In this paper, we describe the design and implementation of our Co-Verification systems.