A Novel Network Architecture Support for Fast Reconfiguration

Author

Kuo, Jenny Yi-Chun ; Elgindy, Hossam ; Ku, Anderson Kuei-An

fYear

2007

fDate

12-14 Dec. 2007

Firstpage

353

Lastpage

356

Abstract

The aim of this paper is to present a novel reconfigurable architecture support which provides efficient access to noncontiguous locations in an array-like structure, whether it be memories or configurable logic blocks (Claw) in reconfigurable systems. This distribution tree (distTree) architecture serves as a mean of address resolution so that no addressing information is required externally or explicitly. It not only reduces the amount of information transferred but also reduces the time for address resolution significantly. A software and a hardware simulators were developed to test the correctness, performance, and hardware resources required for distTree. We found from our simulators that the run-time overhead for address resolution is close to none in most cases while occupying a reasonable amount of hardware area.

Keywords

reconfigurable architectures; address resolution; distribution tree architecture; fast reconfiguration; network architecture support; reconfigurable systems; Australia; Computer architecture; Computer science; Counting circuits; Delay; Field programmable gate arrays; Hardware; Logic arrays; Reconfigurable logic; Runtime;

fLanguage

English

Publisher

ieee

Conference_Titel

Field-Programmable Technology, 2007. ICFPT 2007. International Conference on

Conference_Location

Kitakyushu

Print_ISBN

978-1-4244-1472-7

Electronic_ISBN

978-1-4244-1472-7

Type

conf

DOI

10.1109/FPT.2007.4439284

Filename

4439284