DocumentCode
2877074
Title
A 64Kb full CMOS RAM with divided word line structure
Author
Yoshimoto, Masahiko ; Anami, K. ; Shinohara, Hirofumi ; Yoshihara, Tatsuhiko ; Takagi, Hiroyuki ; Nagao, Shijo ; Kayano, S. ; Nakano, T.
Author_Institution
Mitsubishi LSI Research and Development Laboratory, Itami, Japan
Volume
XXVI
fYear
1983
fDate
23-25 Feb. 1983
Firstpage
58
Lastpage
59
Abstract
An 8K×8b N-well CMOS static RAM with a divided word line architecture which decreases both the column current and word line delay will be described. The RAM achieves an access time of 50ns while dissipating 100mW. The use of molybdenum silicide as a substitute for the second polysilicon layer will be reviewed.
Keywords
CMOS process; CMOS technology; Capacitance; Circuits; Clocks; Decoding; Delay; Large scale integration; Random access memory; Read-write memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location
New York, NY, USA
Type
conf
DOI
10.1109/ISSCC.1983.1156503
Filename
1156503
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