Title :
General estimation of Stress Induced Voiding for vias connected to large Cu plate
Author :
Huang, Clement ; Liang, James W. ; Juan, Alex ; Su, K.C.
Author_Institution :
United Microelectron. Corp., Hsinchu, Taiwan
Abstract :
Stress Induced Voiding is strongly influenced by test key structure. Plate size shows vacancy reservoir effect. Void under via is quite observed in Plate_Below structure, and it could caused by the high local stress concentration at via bottom. Larger metal width/length & smaller via dimension will induce poor SM performance. Topological Layout Rule of redundant via placement is suitable for Cu generation (0.13~0.065um).
Keywords :
copper; integrated circuit interconnections; integrated circuit reliability; plates (structures); vacancies (crystal); voids (solid); Cu; plate size; plate-below structure; reliability; stress induced voiding; vacancy reservoir effect; via dimension; Copper; Periodic structures; Reliability; Resistance; Stress;
Conference_Titel :
Physical and Failure Analysis of Integrated Circuits (IPFA), 2011 18th IEEE International Symposium on the
Conference_Location :
Incheon
Print_ISBN :
978-1-4577-0159-7
Electronic_ISBN :
1946-1542
DOI :
10.1109/IPFA.2011.5992745
