System Level Impact of Stitching Vias and Capacitors for High-Speed Differential Links

This paper discusses the link-level impact and design guidelines of stitching vias and stitching capacitors for highspeed differential systems. Consistent results were obtained between test board VNA/TDR characterization and 3D full-wave EM modeling. While the number and distance of stitching vias and decaps have little or no impact on differential mode crosstalk and ISI, their impact on common-mode crosstalk and ISI is high. Furthermore, effectiveness of stitching capacitors is relatively low at high frequencies comparing to stitching vias. Link-level time domain analysis was also performed to confirm the impact. Finally, a routing guideline for platform design was recommended for stitching vias and capacitors.