• DocumentCode
    2877385
  • Title

    A high-speed and low-latency Reed-Solomon decoder based on a dual-line structure

  • Author

    Kang, Hyeong-Ju ; Park, In-Cheol

  • Author_Institution
    Dept. of EE, KAIST, 373-1, Guseong-dong, Yuseong-gu, Daejeon, Korea
  • Volume
    3
  • fYear
    2002
  • fDate
    13-17 May 2002
  • Abstract
    This paper presents a new decoding structure of Reed-Solomon ( RS) codes that are widely used for channel coding. Although many decoding structures have been developed, the serial structures have long latency and the parallel structures are not fast enough to deal with the demands of high-speed decoding. To achieve both short latency and fast ope,ration, the summation of the products of syndromes is eliminated and the difference used to calculate the error locator polynomial is incrementally updated. The proposed structure called a dual-line structure can operate as fast as the serial structure and has as short latency as the parallel structure. In addition, the dual-line structure is regular and easy to implement. Experimental results confirm these advantages at the cost of a small hardware increase.
  • Keywords
    Decoding; Hardware design languages; Lead; Logic gates; Registers;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Acoustics, Speech, and Signal Processing (ICASSP), 2002 IEEE International Conference on
  • Conference_Location
    Orlando, FL, USA
  • ISSN
    1520-6149
  • Print_ISBN
    0-7803-7402-9
  • Type

    conf

  • DOI
    10.1109/ICASSP.2002.5745325
  • Filename
    5745325