A merged multiplier-accumulator for high speed signal processing applications

In an attempt to improve the speed of signal processing VLSI systems, a new architecture for high speed Multiply Accumulate Units is proposed. The architecture is based on Binary trees constructed using 4-2 compressor circuits. Increasing the speed of operation is achieved by taking advantage of the available free input lines of the 4-2 compressors, which result from the parallelogram shape of the generated partial products, and using the bits of the accumulated value to fill in these gaps. This results in merging the accumulation operation within the multiplication process. An 8-bit Multiplier Accumulator prototype circuit using the proposed architecture is prototyped in 0.35 micron double metal CMOS technology and simulated using hspice. Simulation results at 3.3 V show that the proposed architecture has a delay of 4.26 ns with a 16.8 delay savings. At 150 MHz operating frequency, the power consumption is 324 mWatts with a 23.04% power saving compared to other architectures not using the merging technique.