Title :
ON THE TESTABLE DESIGN OF BILATERAL BIT-LEVEL SYSTOLIC ARRAYS
Author :
Bandyopadhyay, Subir ; Bhattacharya, Bhargab B.
Keywords :
Automatic testing; Computer science; Hardware; Logic arrays; Logic testing; Parallel algorithms; Performance evaluation; Signal processing; Systolic arrays; Very large scale integration;
Conference_Titel :
Test Conference, 1991, Proceedings., International
Print_ISBN :
0-8186-9156-5
DOI :
10.1109/TEST.1991.519770
