DocumentCode :
2877711
Title :
Exploring a low-cost inter-layer communication scheme for 3D networks-on-chip
Author :
Rahmani, Amir-Mohammad ; Liljeberg, Pasi ; Plosila, Juha ; Tenhunen, Hannu
Author_Institution :
Turku Centre for Comput. Sci. (TUCS), Turku, Finland
fYear :
2010
fDate :
23-24 Sept. 2010
Firstpage :
163
Lastpage :
166
Abstract :
In this paper, a low-cost 3D NoC architecture based on Bidirectional Bisynchronous Vertical Channels (BBVC) is proposed as a solution to mitigate high area footprints of vertical interconnects. Dynamically self-configurable BBVCs, which can transmit flits in either direction, enable a system to benefit from a high-speed bidirectional channel instead of a pair of unidirectional channels for inter-layer communication. In this architecture, low-latency attribute of the interconnect TSVs enables the system to support a higher frequency for vertical channels, better bandwidth utilization, lower area footprint, and improved routability. In addition, an enhanced BBVC-based communication scheme, called Direct Vertical Channel Access, is presented to enable an express inter-layer communication. Experimental results verify that the proposed architecture can reduce up to 47% TSV area footprint with a negligible performance degradation.
Keywords :
computer networks; network-on-chip; 3D NoC architecture; 3D networks-on-chip; BBVC; bandwidth utilization; bidirectional bisynchronous vertical channels; improved routability; interlayer communication; low-cost inter-layer communication scheme; vertical interconnects; Bandwidth; Clocks; Computer architecture; Integrated circuit interconnections; Routing; Three dimensional displays; Through-silicon vias;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer Architecture and Digital Systems (CADS), 2010 15th CSI International Symposium on
Conference_Location :
Tehran
Print_ISBN :
978-1-4244-6267-4
Type :
conf
DOI :
10.1109/CADS.2010.5623588
Filename :
5623588
Link To Document :
بازگشت