DocumentCode :
2877716
Title :
A 90ns 256K × 1b DRAM with double level A1 technology
Author :
Fujii, Teruya ; Mitake, K. ; Tada, Kazuki ; Inoue, Yasuyuki ; Watanabe, Hiromi ; Kudo, O. ; Yamamoto, Hiroshi
Author_Institution :
Nippon Electric Co., Ltd., Kanagawa, Japan
Volume :
XXVI
fYear :
1983
fDate :
23-25 Feb. 1983
Firstpage :
226
Lastpage :
227
Abstract :
A 256K DRAM with 90 
access time using double level aluminum technology will be reported. Employed are 1.3μ design rules and 160Å effective oxide thickness in a cell area of 66.5μ2. Chip area is 34mm2.
access time using double level aluminum technology will be reported. Employed are 1.3μ design rules and 160Å effective oxide thickness in a cell area of 66.5μ2. Chip area is 34mm2.Keywords :
Assembly; Electronics packaging; Error analysis; Mass production; Paper technology; Plastics; Random access memory; Read-write memory; Redundancy; Temperature;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
Conference_Location :
New York, NY, USA
Type :
conf
DOI :
10.1109/ISSCC.1983.1156541
Filename :
1156541
Link To Document :
