Thermal and Electrical Performance Enhancement with a Cost-Effective Packaging for High Speed Memory Chips

By properly incorporating wafer level package (WLP) and chip embedded processes, a type II chip-in-substrate package (CiSP) without ultra-thin chips is developed for high speed memory devices in this paper. According to the design concept of the type II CiSP, a hybrid process using build-up technologies in wafer level and COG-based (chip-on-glass) transfer bonding is explored to implement the JEDEC-compliant DDR II component. It can be seen that the cost advantages of PCB-like CiSP and the electrical performance of WLP can be achieved simultaneously by adopting this proposed solution. A test vehicle of DDRII-667 memory chips provided by ProMos Technologies Inc. was studied here to demonstrate the feasibility of this developed packaging. Compared with the type I CiSP and the current w-BGA package, the performance is thermally and electrically enhanced.