Drain bias stress-induced degradation in amorphous silicon thin film transistors with negative gate bias

In this study, degradation of amorphous silicon thin film transistors (a-Si TFTs) under drain bias (V_d) stresses with fixed negative gate bias (V_g) has been investigated. For DC V_d stress, state creation mechanism dominates the threshold voltage (V_th) degradation for relative large negative V_gd (V_g-V_d) while state creation and/or electron trapping dominates for positive V_gd. For AC V_d stress, state creation, electron trapping and hole trapping contribute to the degradation. Dominant mechanism depends on stress time, frequency and the polarity of V_gd. Decreasing stress voltage suppresses state creation and/or hole trapping for -V_gd condition, but enhances state creation and/or electron trapping for +V_gd condition.