• DocumentCode
    2878075
  • Title

    A 20ns CMOS functionable gate array with a configurable memory

  • Author

    Sano, Tomomi ; Matsukuma, S. ; Hashimoto, Koji ; Ohuchi, Y. ; Kudo, O. ; Yamamoto, Hiroshi

  • Author_Institution
    Nippon Electric Co., Ltd., Kanagawa, Japan
  • Volume
    XXVI
  • fYear
    1983
  • fDate
    23-25 Feb. 1983
  • Firstpage
    146
  • Lastpage
    147
  • Abstract
    A CMOS gate array with 4,368 gates and 2,304 bits of configurable memory, using 1.5μm design rules, will be discussed. The memory can change word × bit configuration as well as to increase the gate array function.
  • Keywords
    Artificial intelligence; Bonding; Chip scale packaging; Delay; Inverters; Metallization; National electric code; Pins; Variable structure systems; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1983 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1983.1156558
  • Filename
    1156558
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2878075