Controlling Top Package Warpage for POP Applications

The need to integrate devices in the vertical dimension to reduce space, thickness, and cost for handheld applications has fueled enormous growth of what can be termed 3D packaging. Due to testability, business flow, and configuration flexibility issues, the package on package (POP) vertical stacking solution has emerged as the preferred method to stack mobile phone logic processor with memory. The POP solution typically consists of the logic processor in the bottom package and memory device stack in the top package. The bottom package has land pads on the top perimeter in order to allow top package to be mounted and reflowed above. Both packages must be capable of being placed on the PC board and reflowed simultaneously to each other and to the board. Control of the top and bottom package warpage is a critical issue impacting board mount yields and adoption. A series of experiments were performed to determine the impact of different materials and construction on the warpage of the top package at reflow temperature. From this work certain trends are apparent and can be used to optimize the top package warpage to assure compatibility of warpage with the bottom POP and high yields during the simultaneous reflow of the POP stack to the motherboard.