DocumentCode
2878539
Title
Effect of Power and Ground Co-Reference to Performance of Memory Interface I/Os in FPGA and Structural ASIC Device Packages
Author
Shi, Hong ; Jiang, Xiaohong ; Yew, Yeehuan
Author_Institution
Altera Corp., San Jose
fYear
2007
fDate
May 29 2007-June 1 2007
Firstpage
804
Lastpage
809
Abstract
In this paper, we present a summary of FPGA package development with focus on PDN and I/O co-design for optimal performance. Extensive simulation and characterization study are performed to address the effect of power and ground co-reference to memory interface I/O performance in large scale FPGA and structural ASIC devices.
Keywords
application specific integrated circuits; field programmable gate arrays; FPGA; I/O co-design; PDN; memory interface; power and ground co-reference; structural ASIC device packages; Analytical models; Application specific integrated circuits; Crosstalk; Field programmable gate arrays; Packaging; Power distribution; Power system modeling; Power transmission lines; Silicon; Stripline;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
Conference_Location
Reno, NV
ISSN
0569-5503
Print_ISBN
1-4244-0985-3
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2007.373890
Filename
4249976
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