• DocumentCode
    2878678
  • Title

    Posibits, negabits, and their mixed use in efficient realization of arithmetic algorithms

  • Author

    Jaberipur, G. ; Parhami, B.

  • Author_Institution
    Dept. of Electr. & Comput. Engr., Shahid Beheshti Univ., Tehran, Iran
  • fYear
    2010
  • fDate
    23-24 Sept. 2010
  • Firstpage
    3
  • Lastpage
    9
  • Abstract
    Positively weighted and negatively weighted bits (posibits, negabits) have been used in the interpretation of 2´s-complement, negative-radix, and binary signed-digit number representation schemes as a way of facilitating the development of efficient arithmetic algorithms for various application domains. In this paper, we show that a more general view of posibits and negabits, along with their mixed use in any combination (using inverse encoding for negabits), unifies a number of diverse implementation schemes, while at the same time making the resultant designs more efficient by avoiding custom or modified hardware elements and restricting the implementation to the use of standard arithmetic cells. Such standard cells have been highly optimized and are continually improving due to their wide applicability. Other practical benefits of our formulation include facilitation of low-voltage and low-power design, again due to the widespread availability of standard cells in variants optimized for low-voltage operation or energy economy. Pedagogical benefits include more intuitive explanations for a number of widely used transformations, such as Booth´s recoding and column compression.
  • Keywords
    arithmetic codes; residue number systems; Booths recoding; arithmetic algorithms; binary signed digit number representation; diverse implementation; efficient arithmetic algorithms; efficient realization; energy economy; low voltage operation; modified hardware elements; negatively weighted bits; pedagogical benefits; positively weighted bits; standard arithmetic cells; Adders; Algorithm design and analysis; Compressors; Encoding; Hardware; Logic gates; Signal processing algorithms;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer Architecture and Digital Systems (CADS), 2010 15th CSI International Symposium on
  • Conference_Location
    Tehran
  • Print_ISBN
    978-1-4244-6267-4
  • Type

    conf

  • DOI
    10.1109/CADS.2010.5623646
  • Filename
    5623646