Title :
A capacitance coupled bit line cell for Mb level DRAMs
Author :
Taguchi, M. ; Audo, S. ; Hijiya, S. ; Nakamura, T. ; Economo, S. ; Yabu, T.
Author_Institution :
Fujitsu Semicond. Devices Lab., Atsugi, Japan
Keywords :
Capacitors; Circuit testing; Coupling circuits; Laboratories; MOS devices; Parasitic capacitance; Random access memory; Semiconductor devices; Substrates; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156600
