Improvement of JEDEC Drop Test in SJR Qualification through Alternative Test Board Design

Solder joint reliability (SJR) under drop impact is a big concern for hand-held device such as mobile phone and PDA. In the semiconductor industry, generally board level drop test is used to assess solder joint performance under drop impact. JEDEC published a standard on drop test which defines drop impact pulse and test board configuration, and thus when the standard is strictly followed SJR drop test carried out by different semiconductor component manufacturers can be compared. However when the JEDEC drop test board is used for package qualification, there are some limitations. Firstly, the JEDEC test board provided so many solder joint loading conditions which are sometimes not necessary because the main drop test indicator is the earliest drop test failure which is dominated by the worst loading condition. Secondly, so many loading conditions reduce the sample size of each loading condition when the data are statistically processed. Here we propose an alternative test board design with only one loading condition and sufficiently large sample size, which is more suitable for package qualification statistically. Except the board shape and size and package component layout, all other board design requirement strictly follows the JEDEC standard so that it can be easily implemented.