Electrical Characterization and Design Optimization of Embedded Chip in Substrate Cavities

Endless demands for digital convergence by ultra-miniaturization, increased functionality, better performance and low cost in both mobile and desktop systems are driving the needs for new and unique solutions in system integration. The requirements of future electronic systems include faster, smaller, lighter and thinner products. Advanced electronic packaging caters to these ultra-miniaturization and performance needs. The approach of embedding passive components has been in the fray for a while now and the relatively newer perspective to sustain the miniaturization trend efficiently is by embedded active chips as well. This paper discusses the electrical design aspects of embedded actives dealing with the chip-last methodology of embedding dies in particular. The various issues that are expected to surface are made clear through electromagnetic simulations using 3D solver tools. The transmission lines forming the substrate wiring when the cavities are made are analyzed comprehensively. A test vehicle is fabricated based on this new approach and preliminary measurement results are also included in this paper.