• DocumentCode
    2879365
  • Title

    Implementation and evaluation of a parallel PMS simulator

  • Author

    Rao, Manohar ; Segall, Zary

  • Author_Institution
    Carnegie Mellon Univ., Pittsburgh, PA, USA
  • fYear
    1990
  • fDate
    7-9 Mar 1990
  • Firstpage
    408
  • Lastpage
    416
  • Abstract
    The sources of parallelism in an event-driven simulator have been investigated. First, a simple and straightforward parallelization strategy was implemented. It was observed that this strategy did not provide sufficient parallelism. Then the advance scheduling strategy was developed, which has yielded a significantly higher degree of parallelism. The main contribution of this research has been the development of this advance scheduling strategy. This strategy trades a small amount of inaccuracy in the simulation results for a large gain in the amount of parallelism extracted from the simulator. This strategy can be effectively applied for statistical simulators, because the statistical methods of simulation themselves introduce variations in the results. It was observed that, with a proper choice for the overlap distance, the error in the final results is comparable to the variation in the results introduced by the statistical simulation methods employed. A modified implementation of the event queue (Runqueue), which exploits the disorder in event scheduling created by the advance scheduling strategy, is presented. This implementation should significantly reduce contention for the Runqueue. A simulation model was implemented to simulate a distributed memory architecture proposed by D. Black, Z. Segall, and L. Rudolph. With the help of this simulation model, extensive experiments can be conducted to determine the strengths and weaknesses of the proposed architecture
  • Keywords
    digital simulation; parallel processing; performance evaluation; Runqueue; advance scheduling strategy; distributed memory architecture; event-driven simulator; parallel PMS simulator; parallelism; parallelization strategy; processor memory switch simulator; Analytical models; Computational modeling; Computer architecture; Computer performance; Computer science; Costs; High performance computing; Microprocessors; Multiprocessing systems; Parallel processing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Databases, Parallel Architectures and Their Applications,. PARBASE-90, International Conference on
  • Conference_Location
    Miami Beach, FL
  • Print_ISBN
    0-8186-2035-8
  • Type

    conf

  • DOI
    10.1109/PARBSE.1990.77166
  • Filename
    77166