Thermo-Mechanical Analysis of Thru-Silicon-Via Based High Density Compliant Interconnect

In this paper, detailed 3D FEM thermo-mechanical analysis is performed on a chip stack that utilizes the smart three axis compliant (STAC) interconnect, a TSV based ultra-high density compliant interconnect. These interconnects are microstructurally engineered to accommodate relative displacements between ultra-thin TSV based silicon chips and substrates to which they are bonded without transferring significant stress to the die itself. The paper will first cover 3D numerical model of the TiW bi-metal layer compliant beam built with opposing stresses to establish z-axis lift-height that compares well with analytical results. With this validated model, a force-deflection curve is established for a 125 mumtimes25 mumtimes0.8 mum TiW free beam with 1 GPa stress built into its two metal layers (-500 MPa in the bottom layer and +500 MPa in the top layer). This enables numerical characterization of the compliancy of a single interconnect. This analysis is followed by thermo-mechanical analysis of a unit cell STAC interconnect (TSV, copper bond pad and the compliant beam) built on a 50 mum thick silicon die. Particular attention is given to stresses formed in the TSV copper column when temperature is varied from -40degC to 150degC. Finally experimental results performed on a successfully fabricated STAC interconnect based Si-Glass stacked die is presented and a numerical model of this chip stack is built to capture the top ultra-thin glass die deformation when temperature is varied from 20degC to 130degC.