Title :
A VLSI communication processor designed for testability
Author :
Sacarisen, S. ; Stambaugh, M. ; Lou, P. ; Khosrovi, A. ; Ki Chang
Author_Institution :
Texas Instruments, Inc., Houston, TX, USA
Abstract :
A 16b processor for control of digital communication networks, with 2186 bytes of RAM will be discussed. The chip features include instruction fault detection, I/O parity check/ generation and special test modes.
Keywords :
Circuit faults; Circuit noise; Circuit testing; Decoding; Hardware; Logic testing; Process design; Read only memory; Registers; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156646
