Title :
A 25/50MHz dual-mode parallel multiplier/accumulator
Author :
Welten, F. ; Lohstroh, J. ; Linssen, A.
Author_Institution :
Philips Res. Labs., Eindhoven, Netherlands
Abstract :
A 12 × 12 parallel multiplier/accumulator using standard 3μm bipolar oxide-isolated ISL technology will be described. A gated pipeline-register which can be bypassed allows the chip to be used in a direct mode at a 25MHz rate or in a pipeline mode at a 50MHz clock rate. Power dissipation is 900mW.
Keywords :
Adders; Circuits; Clocks; Delay; Electron devices; Isolation technology; Logic; Pipelines; Registers; Voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156650
