• DocumentCode
    2879578
  • Title

    A 25/50MHz dual-mode parallel multiplier/accumulator

  • Author

    Welten, F. ; Lohstroh, J. ; Linssen, A.

  • Author_Institution
    Philips Res. Labs., Eindhoven, Netherlands
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    86
  • Lastpage
    87
  • Abstract
    A 12 × 12 parallel multiplier/accumulator using standard 3μm bipolar oxide-isolated ISL technology will be described. A gated pipeline-register which can be bypassed allows the chip to be used in a direct mode at a 25MHz rate or in a pipeline mode at a 50MHz clock rate. Power dissipation is 900mW.
  • Keywords
    Adders; Circuits; Clocks; Delay; Electron devices; Isolation technology; Logic; Pipelines; Registers; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156650
  • Filename
    1156650
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2879578