Title :
A 32b NMOS microprocessor with a large register file
Author :
Sherburne, R. ; Katevenis, Manolis ; Patterson, Dean ; Sequin, C.
Author_Institution :
University of California, Berkeley, CA, USA
Abstract :
This paper will discuss the characteristics of two scaled versions of a 32b reduced instruction set computer. A 4μm version (58mm2) runs at 8MHz within 5% of expected speed, using 1.25W. The 3μm version, for which no additional simulation was provided, operates at 12MHz using 1.8W. Its size is 32mm2.
Keywords :
Circuits; Decoding; Delay; MOS devices; Microprocessors; Pipeline processing; Programmable logic arrays; Reduced instruction set computing; Registers; Timing;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156668
