DocumentCode :
2880036
Title :
A burst-mode LSI equalizer with analog-digital building blocks
Author :
Hino, Y. ; Chujo, Takeshi ; Ueno, N. ; Fujita, Kinya ; Yamamoto, Manabu ; Yamaguchi, Kazuhiro ; Kikuchi, Hiroaki
Author_Institution :
Fujitsu, Ltd./Labs., Kawasaki, Japan
Volume :
XXVII
fYear :
1984
fDate :
22-24 Feb. 1984
Firstpage :
238
Lastpage :
239
Abstract :
The development of a 200Kb/s digital subscriber loop equalizer using an analog-digital standard cell building block design system will be described. The circuit uses a 2μm CMOS, a single 5V suoply, and includes 40dB 
AGC and bridged tap equalizers.
AGC and bridged tap equalizers.Keywords :
Analog-digital conversion; Bit rate; Circuit testing; Digital control; Equalizers; Large scale integration; Read only memory; Resistors; Software libraries; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1984.1156673
Filename :
1156673
Link To Document :
