Title :
A VLSI delay commutator for FFT implementation
Author :
Swartzlander, E. ; Young, William ; Joseph, Sadiku
Author_Institution :
TRW Defense Systems Group, Redondo Beach, CA, USA
Abstract :
The implementation of a 108,000 transistor delay/commutator circuit for realization of FFT processors achieving data rates of up to 40MHz, will be described. The circuit contains 12,288 shift register stages and about 2000 logic gates, and implemented with 2.5μm CMOS standard cell technology.
Keywords :
Acoustic signal processing; Counting circuits; Delay; Digital signal processing chips; Radar signal processing; Shift registers; Signal processing algorithms; Speech processing; Switches; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156682
