• DocumentCode
    2880264
  • Title

    An experimental 1Mb DRAM with on-chip voltage limiter

  • Author

    Itoh, Kenji ; Hori, R. ; Jun Etoh ; Asai, Satoshi ; Hashimoto, Noriaki ; Yagi, Keita ; Sunami, H.

  • Author_Institution
    Hitachi Central Res. Lab., Tokyo, Japan
  • Volume
    XXVII
  • fYear
    1984
  • fDate
    22-24 Feb. 1984
  • Firstpage
    282
  • Lastpage
    283
  • Abstract
    This paper will report on an experimental 21μm2cell, single 5V 1Mb NMOS DRAM. Typical clata are: access time 90ns, power dissipation 300mW at 260ns cycle time. Chip area is 46mm2
  • Keywords
    Capacitance; Capacitors; Circuits; Decoding; Power dissipation; Random access memory; Read-write memory; Signal to noise ratio; Switches; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
  • Conference_Location
    San Francisco, CA, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1984.1156686
  • Filename
    1156686
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2880264