DocumentCode :
2880466
Title :
A CMOS ethernet serial interface chip
Author :
Haw-Ming Haung ; Banatao, D. ; Perlegos, G. ; Tsing-Ching Wu ; Te-Long Chiu
Author_Institution :
SEEQ Technology, Inc., San Jose, CA, USA
Volume :
XXVII
fYear :
1984
fDate :
22-24 Feb. 1984
Firstpage :
184
Lastpage :
185
Abstract :
A 10MHz CMOS Ethernet Manchester encoder/decoder will be described. By using a PLL, the device can decode data having 18ns of jitter. The transmitter drives a 78-ohm transceiver cable directly with less than a 0.5ns skew. The chip (2μm/N-well) is 99 × 115mil2and consumes 150mW.
Keywords :
CMOS technology; Circuit noise; Clocks; Delay; Differential amplifiers; Ethernet networks; Filters; Phase locked loops; Transceivers; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
Type :
conf
DOI :
10.1109/ISSCC.1984.1156697
Filename :
1156697
Link To Document :
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