A high speed low complexity Reed-Solomon decoder for correcting errors and erasures

In this paper, a high speed low complexity architecture of Reed-Solomon (RS) code is developed to correct both errors and erasures based on the reformulation inversionless Berlekamp-Massey algorithm. In contrast to the inversionless Berlekamp-Massey architectures [J-H, Jeng et al., 1999], the critical path delay of this decoding algorithm is smaller, and the architecture is extremely regular for VLSI implementation. The proposed decoder has been designed and synthesized for the Xilinx Virtex series FPGAs xcv600-5. The resource consumption is about 60%, and the data processing rates over 340 Mbit/s is realized.