• DocumentCode
    2880614
  • Title

    Effects of Assembly Process Parameters on the Structure and Thermal Stability of Sn-Capped Cu Bump Bonds

  • Author

    Huffman, Alan ; Lueck, Matthew ; Bower, Christopher ; Temple, Dorota

  • Author_Institution
    RTI Int., Research Triangle Park
  • fYear
    2007
  • fDate
    May 29 2007-June 1 2007
  • Firstpage
    1589
  • Lastpage
    1596
  • Abstract
    Non-collapsible Cu-Sn bumps (Cu pillars capped with a thin layer of Sn) have been studied recently as a means to vertically interconnect device layers, achieving 3D integrated circuits. The use of Cu-Sn bump structures is attractive for 3D integration for two primary reasons: 1) the rigid nature of the Cu bump allows for very fine pitch interconnections to be made with less risk of bridging than would exist with collapsible solder bumps, and 2) the joint created when bonding Cu and Cu-Sn bumps remelts at a higher temperature than the formation temperature, which allows for the stacking of multiple layers of devices without disturbing the interconnections achieved in previous bonding events. In order to understand the optimal structure and bonding process for fine pitch Cu-Sn bumps, a study was done to investigate the effects of Sn thickness and bonding pressure on the thickness and chemical composition of the bondline between Cu and Cu-Sn bumps. The thermal stability of the bondline was studied by subjecting bonded test samples to multiple temperature/pressure cycles. The bonding strength was evaluated through die shear tests, and the results were correlated with the parameters of the bump structure and with process parameters.
  • Keywords
    copper; integrated circuit interconnections; integrated circuit metallisation; microassembling; thermal stability; tin; 3D integrated circuits; Cu-Sn; assembly process parameter; bonding pressure; bonding process; bump bond; die shear test; fine pitch bump; non-collapsible bumps; optimal structure; thermal stability; vertically interconnect device layer; Assembly; Bonding; Circuit stability; Integrated circuit interconnections; Stacking; Temperature; Testing; Thermal stability; Three-dimensional integrated circuits; Tin;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
  • Conference_Location
    Reno, NV
  • ISSN
    0569-5503
  • Print_ISBN
    1-4244-0985-3
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2007.374007
  • Filename
    4250093