Title :
A VLSI image pipeline processor
Author :
Nukiyama, T. ; Kusano, Tomohiro ; Matsumoto, Kaname ; Kurokawa, Haruhisa ; Hoshi, T. ; Goto, Hiromi ; Temma, T.
Author_Institution :
NEC Corp., Kawasaki, Japan
Abstract :
A 6.9mm×7mm chip with 115K transistors, produced in 1.75μm E/D NMOS technology, will be covered. Data flow architecture with a 10MHz clock rate enables a 3×3 convolution of a 512 × 512 gray image to be performed in 3 seconds by one chip or 1:1 seconds using three cascaded chips.
Keywords :
Computer architecture; Convolution; Digital images; Integrated circuit synthesis; Integrated circuit technology; Parallel processing; Pipeline processing; Pixel; Testing; Very large scale integration;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1984 IEEE International
Conference_Location :
San Francisco, CA, USA
DOI :
10.1109/ISSCC.1984.1156719
