Title :
A 280ps Josephson 4b × 4b parallel multiplier
Author :
Jun´ichi Sone ; Jaw-Shen Tsai ; Ema, S. ; Abe, H.
Author_Institution :
NEC Microelectronics Research Labs., Kawasaki, Japan
Abstract :
A 4b×4b multiplier with 350ps multiplication time and 1mW dissipation that has been built with 249 resistor-coupled Josephson logic gates will be described. Circuits were fabricated in a Pb-alloy process with 5μ minimum line widths and junction diameters.
Keywords :
Arithmetic; Circuit testing; Delay effects; Delay estimation; Delay lines; Electrodes; Power dissipation; Propagation delay; Semiconductor device measurement; Tin;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156724
