• DocumentCode
    2881166
  • Title

    A single chip 80b floating point processor

  • Author

    Takeda, Kenji ; Ishino, F. ; Ito, Yu ; Kasai, Ryouhei ; Nakashima, Takayoshi

  • Author_Institution
    NTT Atsugi Electrical Communication Laboratory, Kanagawa, Japan
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    16
  • Lastpage
    17
  • Abstract
    The application of 1.2μ N-well CMOS technology in a 5.6 MFLOP 80b floating-point processor chip will be described. The chip, which includes 50K gates and 15Kb of memory, was designed, in 11 man months with a heirarchical design automation system.
  • Keywords
    Arithmetic; CMOS logic circuits; CMOS process; CMOS technology; Clocks; Logic testing; Read only memory; Registers; Routing; Wiring;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156738
  • Filename
    1156738
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2881166