An efficient method for compensating the truncation DC-error in a multi-stage digital filter

Binary two´s complement operation in a digital circuit brings increased word length in operation results. In this case, the LSB bit truncation is performed to meet the system requirement. However, truncating the word adds an undesired DC-error to the signal and degrades system performance. To solve this problem, a complementary method is suggested. The proposed scheme improves system performance with a simple method that involves inverting the sign of the truncated signal value. The suggested truncation DC-error reducing method is applied to the multi-stage digital FIR filter implementation on the FPGA and the results are analyzed.