• DocumentCode
    2881261
  • Title

    A 4.5ns 256K CMOS SRAM with tri-level word line

  • Author

    Shinohara, Hirofumi ; Anami, K. ; Ichinose, Kento ; Wada, Tomotaka ; Kohno, Yusuke ; Kawai, Yusuke ; Akasaka, Y. ; Kayano, S.

  • Author_Institution
    Mitsubishi Electric Corporation, Itami, Japan
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    62
  • Lastpage
    63
  • Abstract
    A report on a CMOS SRAM with a peak current of 45mA obtained through the use of an address transition activated circuit combined with a tri-level word-line circuit will be presented.
  • Keywords
    Circuits; Decoding; Differential amplifiers; Electronics packaging; Inverters; Mirrors; Random access memory; Read-write memory; Timing; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156744
  • Filename
    1156744
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2881261