Title :
A 64-bit fast adder with 0.18 μm CMOS technology
Author :
Jin, Zhanpeng ; Shen, Xubang ; Bai, Yongqiang
Author_Institution :
Coll. of Comput. Sci., Northwestern Polytech. Univ., Xi´´an, China
Abstract :
Based on various CMOS technologies: 0.18 mum, 0.15 mum, 0.13 mum and 90 nm, the performance comparisons among three parallel prefix adders with different bit widths are made in this paper. And the adder architecture fit for deep submicron technology is selected according to the impact of connective wires on adder performance. The organization and circuit design of a 64-bit high speed binary parallel adder built in TSMC 2.5 V 0.18 mum IP6M CMOS fabrication technology is presented. Using clock-delayed domino logic, the delay of each stage in the adder is reduced. The addition latency is no more than 668 ps with about 4500 transistors integrated into the area of 0.13 mm2.
Keywords :
CMOS logic circuits; adders; clocks; 0.18 mum; 2.5 V; 64 bit; CMOS technology; IP6M CMOS fabrication technology; clock-delayed domino logic; deep submicron technology; fast adder; high speed binary parallel adder; three parallel prefix adders; transistors; Adders; CMOS technology; Circuit analysis; Clocks; Computer architecture; Computer science; Delay; Educational institutions; Microprocessors; Very large scale integration; Dynamic Domino; clock-delay; prefix adder;
Conference_Titel :
Communications and Information Technology, 2005. ISCIT 2005. IEEE International Symposium on
Conference_Location :
Beijing
Print_ISBN :
0-7803-9538-7
DOI :
10.1109/ISCIT.2005.1567086
