• DocumentCode
    2881366
  • Title

    Different Wire Layouts for CMOS Inductors

  • Author

    Karjalainen, Paivi H. ; Heino, Pekka

  • Author_Institution
    Tampere Univ. of Technol., Tampere
  • fYear
    2007
  • fDate
    May 29 2007-June 1 2007
  • Firstpage
    1846
  • Lastpage
    1850
  • Abstract
    The easiest way to improve the quality and decrease the size of the integrated passive components is to improve their layout. On-wafer CMOS inductors with different layouts of metal coils aimed at optimizing the component characteristics are processed, measured, and analyzed. Narrow extra wires at the edges of spirals and continuous via arrays in the spirals are found to be effective, when peak value of quality factor (Q) and resonance frequency (fres) are considered the critical parameters.
  • Keywords
    CMOS integrated circuits; Q-factor; coils; inductors; wires (electric); CMOS inductors; integrated passive components; metal coils; quality factor; resonance frequency; wire layouts; CMOS process; CMOS technology; Circuits; Conducting materials; Conductivity; Dielectric substrates; Inductors; Resistors; Silicon; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference, 2007. ECTC '07. Proceedings. 57th
  • Conference_Location
    Reno, NV
  • ISSN
    0569-5503
  • Print_ISBN
    1-4244-0985-3
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2007.374048
  • Filename
    4250134
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2881366