Title :
An 80ps 2500-gate bipolar macrocell array
Author :
Horiguchi, Shogo ; Suzuki, M. ; Ichino, H. ; Konaka, Shogo ; Sakai, Tadashi
Author_Institution :
NTT Atsugi Electrical Communication Lab., Kanagawa, Japan
Abstract :
This paper will cover a 2500-gate bipolar array with 80ps delay, which uses a macro cell design and 1μ rules. A 7.5ns 16b multiplier has been realized.
Keywords :
Circuit synthesis; Delay effects; Gallium arsenide; Laboratories; Logic; Macrocell networks; Power dissipation; Resistors; Semiconductor device measurement; Switches;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156752
