• DocumentCode
    2881678
  • Title

    A 20ns static column 1Mb DRAM in CMOS technology

  • Author

    Sato, Kiminori ; Kawamoto, Hiroaki ; Yanagisawa, Kei ; Matsumoto, Tad ; Shimizu, Shogo ; Hori, R.

  • Author_Institution
    Hitachi Device Development Center, Tokyo, Japan
  • Volume
    XXVIII
  • fYear
    1985
  • fDate
    13-15 Feb. 1985
  • Firstpage
    254
  • Lastpage
    255
  • Keywords
    CMOS technology; Capacitance; Circuits; Clocks; Electronics packaging; Energy consumption; Laboratories; Power dissipation; Random access memory; Threshold voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
  • Conference_Location
    New York, NY, USA
  • Type

    conf

  • DOI
    10.1109/ISSCC.1985.1156769
  • Filename
    1156769
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2881678