Title :
A 20ns static column 1Mb DRAM in CMOS technology
Author :
Sato, Kiminori ; Kawamoto, Hiroaki ; Yanagisawa, Kei ; Matsumoto, Tad ; Shimizu, Shogo ; Hori, R.
Author_Institution :
Hitachi Device Development Center, Tokyo, Japan
Keywords :
CMOS technology; Capacitance; Circuits; Clocks; Electronics packaging; Energy consumption; Laboratories; Power dissipation; Random access memory; Threshold voltage;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156769
