Title :
A 50ns 48-term erasable programmable logic array
Author :
Leung, Ruby ; Lee, S.M.
Author_Institution :
Signetics Corp., Sunnyvale, CA, USA
Abstract :
This paper will cover the design of a CMOS EPROM process that serves to implement a 48 P-term AND-OR array with 16 inputs and 8 outputs. The array requires a 20mA quiescent current and 50mA maximum during switching and can be programmed using a conventional 21V EPROM programmer.
Keywords :
CMOS logic circuits; Circuit testing; EPROM; Logic programming; Neodymium; Programmable logic arrays;
Conference_Titel :
Solid-State Circuits Conference. Digest of Technical Papers. 1985 IEEE International
Conference_Location :
New York, NY, USA
DOI :
10.1109/ISSCC.1985.1156773
